FIG. 1 illustrates a receiver for a data transmission system utilizing point-to-point serial interconnects. The input to the receiver 10 is a stream of serial data that has clock information embedded in the signal. A clock/data recovery (CDR) unit 12 recovers the clock from the stream of serial data to generate a receive clock signal RCLK which is used by the receiver 10 to sample and retime the data from the serial stream. The data is then typically converted to a parallel format and passed along to other apparatus such as a crosspoint switch where data from multiple receivers is re-routed to multiple transmitters.
The receiver shown in FIG. 1 may be used in high-speed data transmission systems where the integrity of the incoming signal is degraded by the transmission path between the transmitter and receiver. For example, the signal may be routed from a transmitter on an integrated circuit (IC) mounted on a first printed circuit board (PC board), over traces on the first board, through contacts on a connector that couple the first board to a backplane, across the backplane, through another connector that couples the back plane to a second board, over an additional set of traces on the second board, and finally to the receiver on a second IC. This transmission path results in a high degree of signal loss, with high-frequency components of the signal being more severely attenuated than the low-frequency components. Cross-talk and noise may also be introduced by the backplane system.
To maintain a reliable flow of high-speed data through a noisy and lossy transmission path, the receiver of FIG. 1 may include an equalizer that compensates for signal loss. Most commonly, the equalizer restores a signal's high frequency components that are attenuated by the transmission path. An equalizer may have programmable equalizer settings to allow a system designer to match the amount of equalization to the measured or calculated amount of attenuation caused by the transmission path.